View HFA1405IA_4355300.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 tm caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000 hfa1405 quad, 675mhz, low power, video operational ampli?r the hfa1405 is a quad, high speed, low power current feedback ampli?r built with intersils proprietary complementary bipolar uhf-1 process. these ampli?rs deliver up to 675mhz bandwidth and 2500v/ s slew rate, on only 58mw of quiescent power. they are speci?ally designed to meet the performance, power, and cost requirements of high volume video applications. the excellent gain ?tness and differential gain/phase performance make these ampli?rs well suited for component or composite video applications. video performance is maintained even when driving a back terminated cable (r l = 150 ? ), and degrades only slightly when driving two back terminated cables (r l = 75 ? ). rgb applications will bene? from the high slew rates, and high full power bandwidth. the hfa1405 is a pin compatible, low power, high performance upgrade for the popular intersil ha5025, and for the clc414 and clc415. features low supply current . . . . . . . . . . . . . . . . . 5.8ma/op amp high input impedance . . . . . . . . . . . . . . . . . . . . . . . 1m ? wide -3db bandwidth (a v = +2) . . . . . . . . . . . . . . 675mhz very fast slew rate . . . . . . . . . . . . . . . . . . . . . . 2500v/ s gain flatness (to 50mhz) . . . . . . . . . . . . . . . . . . . . 0.03db differential gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% differential phase . . . . . . . . . . . . . . . . . . . . 0.03 degrees all hostile crosstalk (5mhz). . . . . . . . . . . . . . . . . . -60db pin compatible upgrade to ha5025, clc414, and clc415 applications flash a/d drivers professional video processing video digitizing boards/systems multimedia systems rgb preamps medical imaging hand held and miniaturized rf equipment battery powered communications high speed oscilloscopes and analyzers related literature technical brief tb363 ?uidelines for handling and processing moisture sensitive surface mount devices (smds) pinouts hfa1405 (pdip, soic) top view hfa1405 (ssop) top view ordering information part number temp. range ( o c) package pkg. no. hfa1405ib -40 to 85 14 ld soic m14.15 hfa1405ip -40 to 85 14 ld pdip e14.3 HFA1405IA -40 to 85 16 ld ssop m16.15a ha5025eval high speed op amp dip evaluation board opampssopeval1 high speed op amp ssop evaluation board out 1 -in 1 +in 1 v+ +in 2 -in 2 out 2 out 4 -in 4 +in 4 v- +in 3 -in 3 out 3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + + + - - - + - out 1 -in 1 +in 1 v+ +in 2 -in 2 out 2 out 4 -in 4 +in 4 v- +in 3 -in 3 out 3 1 2 3 4 5 6 7 16 15 14 13 12 11 10 + + + - - - 8 9 nc nc + - data sheet august 2000 file number 3604.6
2 absolute maximum ratings t a =25 o c thermal information voltage between v+ and v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v dc input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v supply differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v output current (note 2) . . . . . . . . . . . . . . . . .short circuit protected 30ma continuous 60ma 50% duty cycle esd rating human body model (per mil-std-883 method 3015.7) . . . 600v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 moisture sensitivity (see technical brief tb363) all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 1 maximum junction temperature (die) . . . . . . . . . . . . . . . . . . . 175 o c maximum junction temperature (plastic package) . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic and ssop - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. notes: 1. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 fo r details. 2. output is short circuit protected to ground. brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) out put current must not exceed 30ma for maximum reliability. electrical speci?ations v supply = 5v, a v = +1, r f = 510 ?, r l = 100 ?, unless otherwise speci?d parameter test conditions (note 4) test level temp ( o c) hfa1405ib (soic) hfa1405ip (pdip) HFA1405IA (ssop) units min typ max min typ max min typ max input characteristics input offset voltage a 25 - 2 5 - 2 5 - 2 5 mv a full - 3 8 - 3 8 - 3 8 mv average input offset voltage drift b full - 1 10 - 1 10 - 1 10 v/ o c input offset voltage common-mode rejection ratio ? v cm = 1.8v a 25 45 48 - 45 48 - 45 48 - db ? v cm = 1.8v a 85 43 46 - 43 46 - 43 46 - db ? v cm = 1.2v a -40 43 46 - 43 46 - 43 46 - db input offset voltage power supply rejection ratio ? v ps = 1.8v a 25 48 52 - 48 52 - 48 52 - db ? v ps = 1.8v a 85 46 48 - 46 48 - 46 48 - db ? v ps = 1.2v a -40 46 48 - 46 48 - 46 48 - db non-inverting input bias current a 25 - 615 - 615 - 615 a a full - 10 25 - 10 25 - 10 25 a non-inverting input bias current drift b full - 5 60 - 5 60 - 5 60 na/ o c non-inverting input bias current power supply sensitivity ? v ps = 1.8v a 25 - 0.5 1 - 0.5 1 - 0.5 1 a/v ? v ps = 1.8v a 85 - 0.8 3 - 0.8 3 - 0.8 3 a/v ? v ps = 1.2v a -40 - 0.8 3 - 0.8 3 - 0.8 3 a/v non-inverting input resistance ? v cm = 1.8v a 25 0.8 1.2 - 0.8 1.2 - 0.8 1.2 - m ? ? v cm = 1.8v a 85 0.5 0.8 - 0.5 0.8 - 0.5 0.8 - m ? ? v cm = 1.2v a -40 0.5 0.8 - 0.5 0.8 - 0.5 0.8 - m ? inverting input bias current a 25 - 2 7.5 - 2 7.5 - 2 7.5 a a full - 5 15 - 5 15 - 5 15 a inverting input bias current drift b full - 60 200 - 60 200 - 60 200 na/ o c inverting input bias current common-mode sensitivity ? v cm = 1.8v a 25 - 3 6 - 3 6 - 3 6 a/v ? v cm = 1.8v a 85 - 4 8 - 4 8 - 4 8 a/v ? v cm = 1.2v a -40 - 4 8 - 4 8 - 4 8 a/v hfa1405
3 inverting input bias current power supply sensitivity ? v ps = 1.8v a 25 - 2 5 - 2 5 - 2 5 a/v ? v ps = 1.8v a 85 - 4 8 - 4 8 - 4 8 a/v ? v ps = 1.2v a -40 - 4 8 - 4 8 - 4 8 a/v inverting input resistance c 25 - 60 - - 60 - - 60 - ? input capacitance b 25 - 1.4 - - 2.2 - - 1.2 - pf input voltage common mode range (implied by v io cmrr, +r in , and -i b-ias cms tests) a 25, 85 1.8 2.4 - 1.8 2.4 - 1.8 2.4 - v a -40 1.2 1.7 - 1.2 1.7 - 1.2 1.7 - v input noise voltage density f = 100khz b 25 - 3.5 - - 3.5 - - 3.5 - nv/ hz non-inverting input noise current density f = 100khz b 25 - 2.5 - - 2.5 - - 2.5 - pa/ hz inverting input noise current density f = 100khz b 25 - 20 - - 20 - - 20 - pa/ hz transfer characteristics open loop transimpedance gain a v = -1 c 25 - 500 - - 500 - - 500 - k ? ac characteristics (note 3) -3db bandwidth (v out = 0.2v p-p , notes 3, 5) a v = -1 b 25 - 420 - - 360 - - 450 - mhz a v = +2 b 25 - 560 - - 400 - - 675 - mhz a v = +6 b 25 - 140 - - 100 - - - - mhz full power bandwidth (v out =5v p-p , notes 3, 5) a v = -1 b 25 - 260 - - 260 - - 290 - mhz a v = +2 b 25 - 165 - - 165 - - 190 - mhz a v = +6 b 25 - 140 - - 100 - - - - mhz gain flatness (v out = 0.2v p-p , notes 3, 5) a v = -1, 25mhz b 25 - 0.03 - - 0.04 - - 0.03 - db a v = -1, 50mhz b 25 - 0.04 - - 0.04 - - 0.06 - db a v = -1, 100mhz b 25 - 0.09 - - 0.06 - - 0.07 - db a v = +2, 25mhz b 25 - 0.03 - - 0.04 - - 0.04 - db a v = +2, 50mhz b 25 - 0.03 - - 0.04 - - 0.08 - db a v = +2, 100mhz b 25 - 0.07 - - 0.06 - - 0.09 - db a v = +6, 15mhz b 25 - 0.08 - - 0.08 - - ? -db a v = +6, 30mhz b 25 - 0.19 - - 0.27 - - ? -db minimum stable gain a full - 1 - - 1 - - 1 - v/v crosstalk (a v = +1, all channels hostile, note 5) 5mhz b 25 - -60 - - -55 - - -59 - db 10mhz b 25 - -56 - - -52 - - -56 - db output characteristics a v = +2 (note 3), unless otherwise speci?d output voltage swing (note 5) a v = -1, r l = 100 ? a25 3 3.4 - 3 3.4 - 3 3.4 - v a full 2.8 3- 2.8 3- 2.8 3- v output current (note 5) a v = -1, r l =50 ? a 25, 85 50 60 - 50 60 - 50 60 - ma a -40 28 42 - 28 42 - 28 42 - ma output short circuit current b 25 - 90 - - 90 - - 90 - ma closed loop output impedance b 25 - 0.2 - - 0.2 - - 0.2 - ? second harmonic distortion (v out =2v p-p , note 5) 10mhz b 25 - -51 - - -51 - - -51 - dbc 20mhz b 25 - -46 - - -46 - - -46 - dbc third harmonic distortion (v out =2v p-p , note 5) 10mhz b 25 - -63 - - -63 - - -63 - dbc 20mhz b 25 - -56 - - -56 - - -56 - dbc electrical speci?ations v supply = 5v, a v = +1, r f = 510 ?, r l = 100 ?, unless otherwise speci?d (continued) parameter test conditions (note 4) test level temp ( o c) hfa1405ib (soic) hfa1405ip (pdip) HFA1405IA (ssop) units min typ max min typ max min typ max hfa1405
4 application information performance differences between packages the ampli?rs comprising the hfa1405 are high frequency current feedback ampli?rs. as such, they are sensitive to feedback capacitance which destabilizes the op amp and causes overshoot and peaking. unfortunately, the standard quad op amp pinout places the ampli?rs output next to its inverting input, thus making the package capacitance an unavoidable parasitic feedback capacitor. the larger parasitic capacitance of the pdip requires an inherently more stable ampli?r, which yields a pdip device with lower performance than the soic and ssop devices - see electrical speci?ation tables for details. because of these performance differences, designers should evaluate and breadboard with the same package style to be used in production. note that the ?ypical performance curves?section has separate pulse and frequency response graphs for each transient characteristics a v = +2 (note 3), unless otherwise speci?d rise and fall times (v out = 0.5v p-p , note 3) a v = +2 b 25 - 0.8 - - 0.9 - - 0.6 - ns a v = +6 b 25 - 2.9 - - 4 - - - - ns overshoot (v out = 0.5v p-p , v in t rise = 1ns, notes 3, 6) a v = -1, +os b 25 - 7 - - 3 - - 2 - % a v = -1, -os b 25 - 8 - - 13 - - 8 - % a v = +2, +os b 25 - 5 - - 7 - - 5 - % a v = +2, -os b 25 - 10 - - 11 - - 5 - % a v = +6, +os b 25 - 2 - - 2 - - - - % a v = +6, -os b 25 - 2 - - 2 - - - - % slew rate (v out =5v p-p , notes 3, 5) a v = -1, +sr b 25 - 2500 - - 2500 - - 2900 - v/ s a v = -1, -sr b 25 - 1900 - - 1900 - - 2500 - v/ s a v = +2, +sr b 25 - 1700 - - 1600 - - 2100 - v/ s a v = +2, -sr b 25 - 1700 - - 1400 - - 1900 - v/ s a v = +6, +sr b 25 - 1500 - - 1000 - - - - v/ s a v = +6, -sr b 25 - 1100 - - 1000 - - - - v/ s settling time (v out = +2v to 0v step, note 5) to 0.1% b 25 - 23 - - 23 - - 30 - ns to 0.05% b 25 - 30 - - 30 - - 33 - ns to 0.025% b 25 - 37 - - 40 - - 50 - ns overdrive recovery time v in = 2v b 25 - 8.5 - - 8.5 - - 8.5 - ns video characteristics a v = +2 (note 3), unless otherwise speci?d differential gain (f = 3.58mhz) r l = 150 ? b 25 - 0.02 - - 0.03 - - 0.02 - % r l =75 ? b 25 - 0.03 - - 0.06 - - 0.03 - % differential phase (f = 3.58mhz) r l = 150 ? b 25 - 0.03 - - 0.03 - - 0.03 - degrees r l =75 ? b 25 - 0.06 - - 0.06 - - 0.06 - degrees power supply characteristics power supply range c 25 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 v power supply current (note 5) a 25 - 5.8 6.1 - 5.8 6.1 - 5.8 6.1 ma/op amp a full - 5.9 6.3 - 5.9 6.3 - 5.9 6.3 ma/op amp notes: 3. the optimum feedback resistor depends on closed loop gain and package type. see the ?ptimum feedback resistor table in the application information section for details. 4. test level: a. production tested; b. typical or guaranteed limit based on characterization; c. design typical for information only. 5. see typical performance curves for more information. 6. undershoot dominates for output signal swings below gnd (e.g., 2v p-p ), yielding a higher overshoot limit compared to the v out =0vto2v condition. see the ?pplication information?section for details. electrical speci?ations v supply = 5v, a v = +1, r f = 510 ?, r l = 100 ?, unless otherwise speci?d (continued) parameter test conditions (note 4) test level temp ( o c) hfa1405ib (soic) hfa1405ip (pdip) HFA1405IA (ssop) units min typ max min typ max min typ max hfa1405
5 package type. graphs not labeled with a speci? package type are applicable to all packages. optimum feedback resistor although a current feedback ampli?rs bandwidth dependency on closed loop gain isn? as severe as that of a voltage feedback ampli?r, there can be an appreciable decrease in bandwidth at higher gains. this decrease may be minimized by taking advantage of the current feedback ampli?rs unique relationship between bandwidth and r f . all current feedback ampli?rs require a feedback resistor, even for unity gain applications, and r f , in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. thus, the ampli?rs bandwidth is inversely proportional to r f . the hfa1405 design is optimized for r f = 402 ? /510 ? /681 ? (pdip/soic/ssop) at a gain of +2. decreasing r f decreases stability, resulting in excessive peaking and overshoot (note: capacitive feedback causes the same problems due to the feedback impedance decrease at higher frequencies). however, at higher gains the ampli?r is more stable so r f can be decreased in a trade-off of stability for bandwidth. the table below lists recommended r f values for various gains, and the expected bandwidth. for good channel-to- channel gain matching, it is recommended that all resistors (termination as well as gain setting) be 1% tolerance or better. note: r f = 500 ? is not the optimum value. it was chosen to match the r f of the clc414 and clc415, for performance comparison purposes. performance at a v = +6 may be increased by reducing r f below 500 ? . non-inverting input source impedance for best operation, the dc source impedance seen by the non-inverting input should be 50 ?. this is especially important in inverting gain con?urations where the non- inverting input would normally be connected directly to gnd. pulse undershoot the hfa1405 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. in this approach, a composite device replaces the traditional pnp pulldown transistor. the composite device switches modes after crossing 0v, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see figure 8 and figure 11). this undershoot isn? present for small bipolar signals, or large positive signals (see figure 6 and figure 7). pc board layout the frequency response of this ampli?r depends greatly on the amount of care taken in designing the pc board. the use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! attention should be given to decoupling the power supplies. a large value (10 f) tantalum in parallel with a small value (0.1 f) chip capacitor works well in most cases. terminated microstrip signal lines are recommended at the input and output of the device. capacitance, parasitic or planned, connected to the output must be minimized, or isolated as discussed in the next section. care must also be taken to minimize the capacitance to ground at the ampli?rs inverting input (-in). the larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and eventual instability. to reduce this capacitance the designer should remove the ground plane under traces connected to -in, and keep connections to -in as short as possible. an example of a good high frequency layout is the evaluation boards shown in figures 3 and 5. driving capacitive loads capacitive loads, such as an a/d input, or an improperly terminated transmission line will degrade the ampli?rs phase margin resulting in frequency response peaking and possible oscillations. in most cases, the oscillation can be avoided by placing a resistor (r s ) in series with the output prior to the capacitance. figure 1 details starting points for the selection of this resistor. the points on the curve indicate the r s and c l combinations for the optimum bandwidth, stability, and settling time, but experimental ?e tuning is recommended. picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. r s and c l form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 560mhz. by decreasing r s as c l increases (as illustrated in the curve), the maximum bandwidth is obtained without table 1. optimum feedback resistor gain (a cl ) r f ( ? ) pdip/soic/ssop bandwidth (mhz) pdip/soic/ssop -1 310/360/432 360/420/450 +1 510 (+r s = 510)/ 464 (+r s = 649)/ 681 (+r s = 806) 300/375/330 +2 402/510/681 400/560/675 +5 na/200/649 na/330/200 +6 500/500/na (note) 100/140/na +10 na/180/681 na/140/120 hfa1405
6 sacrificing stability. in spite of this, bandwidth still decreases as the load capacitance increases. evaluation board the performance of the hfa1405 pdip or soic can be evaluated using the ha5025 evaluation board. the hfa1405ib (soic) requires a soic to dip adaptor like the aries electronics part number 14-350000-10. the ssop version can be evaluated using the opampssopeval board. the schematic for the pdip/soic amplifier 1 and the ha5025eval board layout are shown in figure 2 and figure 3. resistors r f , r g , and +r s may require a change to values applicable to the hfa1405. the schematic for the ssop ampli?r 1 and the opampssopeval board layout are shown in figure 4 and figure 5. resistors r f , r g , and +r s may require a change to values applicable to the HFA1405IA. to order evaluation boards (part number ha5025eval or opampssopeval), please contact your local sales of?e. 0 100 200 300 400 0 10 20 30 40 50 load capacitance (pf) series output resistance ( ? ) 150 250 350 50 a v =+2 figure 1. recommended series output resistor vs load capacitance +5v 10 f 0.1 f gnd gnd -5v 0.1 f10 f 50 ? in out 1 2 3 4 5 6 7 14 13 12 11 10 9 8 - + r f r g figure 2. evaluation board schematic for pdip/soic 50 ? +r s top layout bottom layout figure 3. evaluation board layout for pdip/soic +5v 10 f 0.1 f gnd gnd -5v 0.1 f10 f 49.9 ? in out 1 2 3 4 5 6 7 14 13 12 11 10 9 8 - + figure 4. evaluation board schematic for ssop 49.9 ? r f r g +r s 0 ? 0 ? hfa1405
7 figure 5. evaluation board layout for ssop bottom layout top layout typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d figure 6. small signal pulse response figure 7. large signal positive pulse response figure 8. large signal bipolar pulse response figure 9. small signal pulse response 160 120 80 40 0 -40 -80 -120 -160 output voltage (mv) time (5ns/div.) a v = +2 soic output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = +2 soic output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = +2 soic output voltage (mv) time (5ns/div.) 160 120 80 0 -40 -80 -120 -160 40 a v = -1 soic hfa1405
8 figure 10. large signal positive pulse response figure 11. large signal bipolar pulse response figure 12. small signal pulse response figure 13. large signal pulse response figure 14. frequency response figure 15. frequency response vs feedback resistor typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d (continued) output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = -1 soic output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = -1 soic output voltage (mv) time (5ns/div.) 160 120 80 0 -40 -80 -120 -160 40 a v = +6 soic output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = +6 soic gain phase a v = +2 a v = +6 a v = +2 a v = -1 a v = +6 a v = -1 v out = 200mv p-p 6 3 0 -3 0.3 1 10 100 800 360 270 180 90 0 frequency (mhz) normalized gain (db) normalized phase (degrees) soic phase (degrees) normalized gain (db) frequency (mhz) a v = +2 v out = 200mv p-p 360 270 180 90 0 1 0 2 r f = 500 ? r f = 683 ? r f = 750 ? r f = 1k ? r f = 1.5k ? r f = 1.5k ? r f = 500 ? 1 10 100 800 soic -1 -2 -3 gain phase hfa1405
9 figure 16. gain flatness figure 17. gain flatness vs feedback resistor figure 18. all hostile crosstalk figure 19. settling response figure 20. small signal pulse response figure 21. large signal positive pulse response typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d (continued) 1 10 100 frequency (mhz) normalized gain (db) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 v out = 200mv p-p a v = -1 a v = +2 a v = +6 -0.4 -0.5 -0.6 -0.7 soic a v = +2, soic v out = 200mv p-p r f = 500 ? r f = 683 ? normalized gain (db) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1 10 100 frequency (mhz) -0.6 -0.7 -0.8 r f = 750 ? r f = 1.5k ? r f = 1k ? -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 crosstalk (db) 0.3 1 10 100 200 frequency (mhz) r l = 100 ? r l = soic 0 5 10 15 20 25 30 35 40 45 50 time (ns) settling error (%) 0.2 0.15 0.1 0.05 0.025 0 -0.025 -0.05 -0.1 -0.15 -0.2 v out = 2v a v = +2 soic 160 120 80 40 0 -40 -80 -120 -160 output voltage (mv) time (5ns/div.) a v = +2 ssop output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = +2 ssop hfa1405
10 figure 22. large signal bipolar pulse response figure 23. small signal pulse response figure 24. large signal positive pulse response figure 25. large signal bipolar pulse response figure 26. small signal pulse response figure 27. large signal bipolar pulse response typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d (continued) output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = +2 ssop output voltage (mv) time (5ns/div.) 160 120 80 0 -40 -80 -120 -160 40 a v = -1 ssop output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = -1 ssop output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = -1 ssop output voltage (mv) time (5ns/div.) 160 120 80 0 -40 -80 -120 -160 40 a v = +1 ssop output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = +1 ssop hfa1405
11 figure 28. small signal pulse response figure 29. large signal bipolar pulse response figure 30. small signal pulse response figure 31. large signal bipolar pulse response figure 32. frequency response figure 33. frequency response typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d (continued) output voltage (mv) time (5ns/div.) 160 120 80 0 -40 -80 -120 -160 40 a v = +5 ssop output voltage (v) time (5ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = +5 ssop output voltage (mv) time (10ns/div.) 160 120 80 0 -40 -80 -120 -160 40 a v = +10 ssop output voltage (v) time (10ns/div.) 1.6 1.2 0.8 0 -0.4 -0.8 -1.2 -1.6 0.4 a v = +10 ssop 3 0 -3 -6 normalized gain (db) normalized phase (degrees) 0 90 180 270 360 frequency (mhz) v out = 200mv p-p ssop a v = +2 a v = -1 a v = +1 a v = +2 a v = -1 a v = +1 1 10 100 1000 gain phase 1 0 -1 -2 normalized gain (db) frequency (mhz) v out = 200mv p-p ssop a v = +5 1 10 100 1000 -3 -4 2 3 a v = +10 4 hfa1405
12 figure 34. gain flatness figure 35. full power bandwidth figure 36. all hostile crosstalk figure 37. settling response figure 38. small signal pulse response figure 39. large signal pulse response typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d (continued) 0.1 0 -0.1 -0.2 normalized gain (db) frequency (mhz) 0.2 -0.3 v out = 200mv p-p ssop a v = +1 a v = -1 a v = +2 1 10 200 -0.4 0.3 0.4 100 1 0 -1 -2 normalized gain (db) frequency (mhz) 2 3 -3 -4 4 v out = 5v p-p ssop a v = +2 1 10 100 1000 a v = -1 a v = +1 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 crosstalk (db) 0.3 1 10 100 frequency (mhz) r l = 100 ? r l = ssop 30 50 70 20 40 60 time (ns) 10 80 100 90 0.1 0.05 -0.025 0 0.025 -0.05 -0.1 settling error (%) v out = 2v a v = +2 ssop time (5ns/div.) output voltage (mv) 160 120 80 40 0 -40 -80 -120 -160 a v = +2 pdip time (5ns/div.) output voltage (v) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 a v = +2 pdip hfa1405
13 figure 40. small signal pulse response figure 41. large signal pulse response figure 42. small signal pulse response figure 43. large signal pulse response figure 44. small signal pulse response figure 45. large signal pulse response typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d (continued) time (5ns/div.) output voltage (mv) 160 120 80 40 0 -40 -80 -120 -160 a v = -1 pdip time (5ns/div.) output voltage (v) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 a v = -1 pdip time (5ns/div.) output voltage (mv) 160 120 80 40 0 -40 -80 -120 -160 a v = +1 pdip time (5ns/div.) output voltage (v) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 a v = +1 pdip a v = +2 pdip time (5ns/div.) output voltage (mv) 160 120 80 40 0 -40 -80 -120 -160 a v = +6 pdip r f = 150 ? time (5ns/div.) output voltage (v) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 a v = +6 pdip r f = 150 ? hfa1405
14 figure 46. small signal pulse response figure 47. large signal pulse response figure 48. frequency response figure 49. frequency response figure 50. full power bandwidth figure 51. frequency response vs feedback resistor typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d (continued) time (5ns/div.) output voltage (mv) 160 120 80 40 0 -40 -80 -120 -160 a v = +6 pdip r f = 500 ? time (5ns/div.) output voltage (v) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 a v = +6 pdip r f = 500 ? 3 0 -3 -6 0.3 1 10 100 800 normalized gain (db) v out = 200mv p-p pdip normalized phase (degrees) 0 90 180 270 360 frequency (mhz) a v = +1 (r f = +r s = 510 ? ) a v = +2 a v = +2 a v = -1 a v = +1 a v = -1 gain phase 3 0 -3 -6 1 10 100 800 normalized gain (db) a v = +6 pdip phase (degrees) 0 90 180 270 360 frequency (mhz) r f = 500 ? r f = 150 ? v out = 200mv p-p r f = 150 ? r f = 500 ? 0.3 gain phase 1 0 -1 -2 1 10 100 800 normalized gain (db) v out = 5v p-p frequency (mhz) a v = +6 a v = +2 a v = -1 2 pdip 3 -3 -4 0.3 a v = +6 (r f = 500 ? ) (r f = 150 ?) 1 0 -1 -2 1 10 100 800 normalized gain (db) frequency (mhz) 2 -3 a v = +2 pdip v out = 200mv p-p r f = 510 ? r f = 422 ? r f = 365 ? r f = 390 ? hfa1405
15 figure 52. gain flatness figure 53. all hostile crosstalk figure 54. settling response figure 55. output voltage vs temperature figure 56. supply current vs supply voltage typical performance curves v supply = 5v, t a = 25 o c, r f = value from the optimum feedback resistor table, r l = 100 ? , unless otherwise speci?d (continued) 0.1 0 -0.1 -0.2 1 10 100 normalized gain (db) frequency (mhz) 0.2 -0.3 v out = 200mv p-p pdip a v = +1 (r f = +r s = 510 ? ) a v = +2 a v = -1 a v = +6 (r f = 150 ? ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 crosstalk (db) 0.3 1 10 100 frequency (mhz) r l = 100 ? r l = pdip 0 5 10 15 20 25 30 35 40 45 50 time (ns) settling error (%) 0.2 0.15 0.1 0.05 0.025 0 -0.025 -0.05 -0.1 -0.15 -0.2 v out = 2v a v = +2 pdip 3.6 3.5 3.4 3.3 3.2 3.1 2.9 2.8 2.7 2.6 -50 -25 0 25 50 75 100 125 temperature ( o c) output voltage (v) 3.0 +v out (r l = 50 ?) +v out (r l = 100 ?) |-v out | (r l = 100 ?) a v = -1 |-v out | (r l = 50 ?) supply voltage ( v) supply current (ma/amplifier) 4.5 6.5 5 5.5 6 7 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 hfa1405
16 die characteristics die dimensions: 79 mils x 118 mils 2000 m x 3000 m metallization: type: metal 1: aicu (2%)/tiw thickness: metal 1: 8k ? 0.4k ? type: metal 2: aicu (2%) thickness: metal 2: 16k ? 0.8k ? substrate potential (powered up): floating (recommend connection to v-) passivation: type: nitride thickness: 4k ? 0.5k ? transistor count: 320 metallization mask layout hfa1405 v- +in1 v+ out1 out4 -in1 -in4 +in4 +in3 +in2 -in3 -in2 out3 out2 v- hfa1405
17 hfa1405 small outline plastic packages (soic) notes: 1. symbols are defined in the ?o series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93
18 hfa1405 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?o series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpen- dicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e14.3 (jedec ms-001-aa issue d) 14 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n14 149 rev. 0 12/93
19 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 hfa1405 shrink small outline plastic packages (ssop) index area e d n 123 -b- 0.17(0.007) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. symbols are defined in the ?o series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ? does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ? dimen- sion at maximum material condition. 10. controlling dimension: inches. converted millimeter dimensions are not necessarily exact. m16.15a 16 lead shrink narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - a2 - 0.061 - 1.54 - b 0.008 0.012 0.20 0.30 9 c 0.007 0.010 0.18 0.25 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.98 4 e 0.025 bsc 0.635 bsc - h 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 l 0.016 0.050 0.41 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 0 5/96

▲Up To Search▲

Price & Availability of HFA1405IA

	To Download HFA1405IA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .